1. Field of the Invention
The present invention relates to a bi-directional driving circuit of a liquid crystal display (LCD) panel, particularly, to a bi-directional driving circuit of an LCD panel that enables bi-directional driving.
2. Background of the Related Art
A typical LCD device includes a driving circuit in an LCD panel, such as a gate driving integrated circuit (IC) and a data driving IC. Also, the LCD device has a fixed driving direction. However, system makers sometimes require various panel configurations.
FIG. 1 is a circuit diagram illustrating a typical polysilicon thin film transistor (TFT) LCD panel.
Referring to FIG. 1, the polysilicon TFT LCD panel includes a pixel array having a plurality of gate lines Gi to Gm arranged to cross a plurality of data lines D1 to Dn, a plurality of first shift registers 11 and buffers 12 for supplying scan signals to each gate line. A plurality of second shift registers 13 and buffers 14 are respectively located in each block of k blocks 2 divided from each data line. The LCD panel also includes a plurality of signal lines S1 to Sn for transmitting video signals output from a digital-to-analog converter (not shown) of a data driving circuit (not shown) to each data line, and a plurality of switching elements 16 for sequentially applying video signals of the signal lines S1 to Sn to the data lines per each block by driving signals output from the second shift registers 13 and buffers 14.
In the driving circuit of the polysilicon LCD panel unlike a conventional amorphous silicon circuit, to reduce the number of contact lines between an external circuit and a panel, the data lines are divided into m blocks while the gate lines are selected, so that a display voltage is sequentially supplied to the data lines. Therefore, the gate lines and the data lines are sequentially driven by the shift registers to display picture images. In this case, since the shift registers implement shifting only in a fixed direction, the degree of freedom in a driving direction required by system makers cannot be provided.
A shift register of the related art LCD panel will be described with reference to FIG. 2.
FIG. 2 is a circuit diagram of a shift register of the related art LCD panel.
A gate pulse or data start pulse (VST), four clock signals CLK1, CLK2, CLK3, and CLK4 having different phases, a power source voltage Vdd and a ground voltage Vss are input to an input terminal of the shift register.
The circuit structure of the shift register includes eight blocks having a similar structure except for a portion where a clock signal is applied.
The first block includes a first p-MOS transistor TFT1 having a source and a gate to which the start pulse VST is applied. Also, a second p-MOS transistor TFT2 having a source is connected to a drain of the first p-MOS transistor TFT1 and a gate to which the fourth clock signal CLK4 is applied. The third p-MOS transistor TFT3 has a source connected to a drain of the second p-MOS transistor TFT2 and a drain connected to the Vss terminal. The fourth p-MOS transistor TFT4 has a source connected to the Vdd terminal, a gate connected to the third clock signal CLK3, and a source connected to the drain of the fourth p-MOS transistor TFT4. The sixth p-MOS transistor TFT6 has a source connected to the first clock signal CLK1, a gate connected to the drain of the second p-MOS transistor TFT2, and a drain connected to the output terminal. The seventh p-MOS transistor TFT7 has a source connected to the output terminal, a gate connected to the drain of the fourth p-MOS transistor TFT4, and a drain connected to the Vss terminal.
A contact node between the drain of the second p-MOS transistor TFT2 and the source of the third p-MOS transistor TFT3 is grounded through a capacitor C1. The gate of the sixth p-MOS transistor TFT6 is connected to the Vss terminal through a second capacitor C2. The gate and the drain of the sixth p-MOS transistor TFT6 are connected with each other through a third capacitor C3. The gate of the seventh p-MOS transistor TFT7 is connected to the Vss terminal through a fourth capacitor C4.
The respective first to eighth blocks are different in that different clock signals are applied to the source of the sixth p-MOS transistor TFT6, the gate of the fourth p-MOS transistor TFT4, and the gate of the second p-MOS transistor TFT2. Also, to the source and the gate of the first p-MOS transistor TFT1 an output terminal of a previous block is connected.
The clock signals from the first block to the eighth block are connected as follows.
The clock signals applied to the source of the sixth p-MOS transistor TFT6 are connected as follows.
The first clock signal CLK1 is applied to the source of the sixth p-MOS transistor TFT6 in the first and the fifth block. The second clock signal CLK2 is applied to the source of the sixth p-MOS transistor TFT6 in the second block and the sixth block. The third clock signal CLK3 is applied to the source of TFT6 in the third block and the seventh block. The fourth clock signal CLK4 is applied to the source of TFT6 in the fourth block and the eighth block.
In blocks one through eight, different clock signals are applied to the gate of the fourth p-MOS transistor TFT4 and are connected as follows.
In the first and fifth blocks, the third clock signal CLK3 is applied to the gate of the fourth p-MOS transistor TFT4. In the second and sixth block, the fourth clock signal CLK4 is applied to the gate of the fourth p-MOS transistor TFT4. In the third and seventh blocks, the first clock signal CLK1 is applied to the gate of the fourth p-MOS transistor TFT4. In the fourth and eight blocks, the second clock signal CLK2 is applied to the gate of the fourth p-MOS transistor TFT4.
In blocks one through eight, different clock signals are applied to the gate of the second p-MOS transistor TFT2 and are connected as follows.
In the first and fifth blocks, the fourth clock signal CLK4 is applied to the gate of the second p-MOS transistor TFT2. In the second and sixth blocks, the first clock signal CLK1 is applied to the gate of the second p-MOS transistor TFT2. In the third and seventh blocks, the second clock signal CLK2 is applied to the gate of the second p-MOS transistor TFT2. In the fourth and eight blocks, the third clock signal CLK3 is applied to the gate of the second p-MOS transistor TFT2.
The operation of the aforementioned level shifter of the related art LCD panel will be described with reference to FIG. 3.
FIG. 3 illustrates input and output waveforms of the shift register of the related art LCD panel.
First, the operation of the first block will be described.
The first p-MOS transistor TFT 1 is turned on when a low level start pulse VST is input in a switch-on state. At this time, since the fourth clock signal CLK4 is input in a switch on state, the second p-MOS transistor TFT2 is also turned on. Accordingly, the node Q becomes low level in a switch on state. This turns on the sixth p-MOS transistor TFT6. As a result, the first clock signal CLK1 is output to the output terminal. In addition, because node QB is high in a switch off state, the seventh p-MOS transistor TFT7 is turned off. As a result, the ground voltage Vss is not applied to the output terminal.
Likewise, in the second block, the output of the first block is low and the first clock signal is low. As a result, the second clock signal CLK2 applied to the source of the sixth p-MOS which was turned on by the Q node and as a result is output through the sixth transistor TFT6.
As shown in FIG. 3, the outputs are sequentially generated from the first block to the eighth block.
However, the related art LCD panel having the driving circuit has several problems.
For example, problems arise in that picture images can be scanned only in an originally designed direction. In other words, the output fails to be generated in the order of the last block to the first block. In this case, it is difficult to freely set a direction of the LCD panel, for example, a landscape or portrait type orientation. Because the system manufacturers who make the products that have LCD panels want a display device capable of scanning images in more than one direction, this is a serious limitation of the related art LCD panels.